1. Field of the Invention
The present invention relates to a semiconductor device using a partial SOI (Silicon On Insulator) substrate having an SOI region and a bulk region and a method of manufacture thereof.
2. Description of the Related Art
The partial SOI substrate has been expected to be promising as those of the next-generation of system LSIs with embedded memories. Up to now, the following methods of manufacturing the partial SOI substrate have been developed.
1. The partial SIMOX (Separation by Implanted Oxygen) method which involves ion implanting oxygen into a portion of a substrate to form a buried dielectric film into the oxygen-implanted portion.
2. The partial epitaxial growth method which involves exposing a portion of an SOI substrate by masking, removing the SOI and a buried dielectric film in the exposed portion, and forming a silicon layer on the exposed portion of the silicon substrate by means of epitaxial growth techniques. This method is disclosed in, for example, Japanese Unexamined Patent Publication No. 8-17694.
3. The partial BOX (Buried OXide) method which involves forming a buried oxide (BOX) layer as a buried dielectric film into a portion of the substrate surface and bonding the BOX side of the substrate to a support substrate.
With the SIMOX method, since oxygen is ion implanted into a portion of the substrate to form the buried dielectric film, crystalline defects will be developed in the silicon layer on the buried dielectric film. Moreover, much contamination is introduced into the silicon layer by transition metals. If, therefore, a semiconductor device is formed in the silicon layer, leakage current would increase. If the semiconductor device is a memory cell, the leakage current would cause a problem of the integrity of data stored in that cell.
With the partial epitaxial growth method, crystalline defects will occur at the interface between an epitaxial layer grown from the SOI layer and an epitaxial layer grown from the silicon substrate exposed as the result of removal of the dielectric film. Moreover, to remove topography introduced by the epitaxial layers so that the surface of one of the epitaxial layers is at the same level as the other layer, difficult planarization technology would be required.
With the partial BOX method, the resulting partial SOI substrate has an interface (the surface of bonding) between the substrate having the partial BOX layer formed in the bulk region and the support substrate. The interface is positioned at substantially the same depth as a well region in which semiconductor devices are formed. Thus, a problem arises in that the interface becomes a source of leakage.
Regardless of whether the substrate structure is bulk or SOI, when the gate sidewall width decreases with decreasing size of MOS transistors, it becomes impossible to ignore the degradation of the performance due to the short-channel effect. To suppress the short-channel effect, it is effective to form shallow source/drain regions.
With the system LSIs with embedded memories, on the other hand, it is required that the power consumption be reduced and the operating speed being increased. Accordingly, it is required that the supply voltage be lowered and the dimensions of devices be scaled down. To reduce the junction capacitance and leakage and make smaller-geometry devices, it is desired to use fully-depleted MOS transistors in which a depletion layer spreads across the entire region in the SOI layer (from drain to source) under a gate electrode. However, since the threshold voltage of the fully-depleted MOS transistors varies according to the thickness of the SOI layer, causing a problem of control of the threshold voltage. It is therefore difficult to produce fully-depleted MOS transistors suitable for practical use.
Furthermore, with the system LSIs with embedded memories, it is required to prevent interference between memory cells formed in the bulk region and logic circuits formed in the SOI region with certainty. For this reason, the demand has increased for developing a semiconductor device suitable for system LSIs with embedded memories which use partial SOI substrates and a method of manufacture thereof.